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Ordering number : ENN*6651
CMOS IC
LC72346W, 72347W
Ultralow-Voltage ETR Controller with On-Chip LCD Driver
Preliminary Overview
The LC72346W and LC72347W are ultralow-voltage electronic tuning microcontrollers that include a PLL that operates up to 250 MHz and a 1/4 duty 1/2 bias LCD driver on chip. This IC includes an on-chip DC-DC converter that can easily create the power supply voltages needed for electronic tuning and contribute to reducing end product costs. This IC is optimal for portable audio equipment that must operate from a single battery. * PLL: Reference frequencies: 1, 3, 3.125, 5, 6.25, 12.5, and 25 kHz * Input frequencies: FM band: 10 to 250 MHz AM band (high): 2 to 20 MHz AM band (low): 0.5 to 10 MHz * Input sensitivity: FM band: 35 mVrms (50 mVrms at 130 MHz or higher frequency) AM band (high, low): 35 mVrms * External reset input: During CPU and PLL operations, instruction execution is started from location 0. * Built-in power-on reset circuit: The CPU starts execution from location 0 when power is first applied. * Halt mode: The controller-operating clock is stopped.
Continued on next page.
Function
* Program memory (ROM): -- 4096 x 16 bits (8K bytes) : LC72346 -- 6144 x 16 bits (12K bytes): LC72347 * Data memory (RAM): -- 256 x 4 bits: LC72346 -- 512 x 4 bits: LC72347 * Cycle time: 40 s (all 1-word instructions) at 75kHz crystal oscillation * Stack: 8 levels * LCD driver: 48 to 80 segments (1/4 duty, 1/2 bias drive) * Interrupts: Two external interrupts Timer interrupts (1, 5, 10, and 50 ms) * A/D converter: Four input channels (6-bit successive approximation conversion) * Input ports: 7 ports (of which three can be switched for use as A/D converter inputs) * Output ports: 6 ports (of which 1 can be switched for use as the beep tone output and 2 are open-drain ports) * I/O ports: 20 ports (of which 8 can be switched for use as LCD ports and as mask options, of which 3 can be switched for use as serial I/O ports) * Serial I/O: One system (LC72347)
Package Dimensions
unit: mm 3190-SQFP64
[LC72346W, 72347W]
12.0 10.0 0.18
1.25
0.5
1.25
0.15
48 49
1.25
33 32
12.0
10.0 0.5
1
16
0.5
0.1 0.5
1.7max
64
1.25
17
SANYO: SQFP64
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N1501TN (OT) No. 6651-1/12
LC72346W, 72347W
Continued from preceding page.
* Backup mode: The crystal oscillator is stopped. * Static power-on function: Backup state is cleared with the PF port * Beep tone: 1.5 and 3.1 kHz * Built-in DC-DC converter: For LCD and A/D converter use (3 V) Can also be used for TU + B creation by using a secondary coil.
* Built-in remaining battery life verification function: Converts the VDD pin level to digital. * Memory retention voltage: 0.5 V or higher * Dedicated memory power supply: The RAM retention time has been increased by the provision of a dedicated memory power supply. * Package: SQFP-64 (0.5-mm pitch) * VDD power supply: 0.9 to 1.8 V
Pin Assignment
XIN TEST1 EO VSS AMIN FMIN VDD BRES COM1 COM2 COM3 COM4 S1 S2 S3 S4 XOUT TEST2 PA3 PA2 PA1 PA0 PB3 PB2 PB1 PB0 PC3 PC2 PC1 PC0 PD3 PD2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
1 2 3 4 5 6 7 8 9
LC72346W LC72347W
10 11 12 13 14 15
33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
S5 S6 S7 S8 S9 S10 S11 S12 S13/PH0 S14/PH1 S15/PH2 S16/PH3 S17/PG0 S18/PG1 S19/PG2 S20/PG3
INT1/PD1
INT0/PD0 PE1 BEEP/PE0 ADI3/PF2 ADI1/PF1 ADI0/PF0 SI1/PK3
SO1/PK2 SCK1/PK1 PK0 VSS VDDRAM VDC3 VDC1 VADJ
No. 6651-2/12
LC72346W, 72347W
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Symbol VDD1 max Maximum supply voltage VDD3 max VDD4 max Input voltage VIN1 VIN2 VOUT1 Output voltage VOUT2 VOUT3 VOUT4 IOUT1 IOUT2 Output current IOUT3 IOUT4 IOUT5 Allowable power dissipation Operating temperature Storage temperature Pdmax Topr Tstg VDD VDDRAM VDC3 FMIN, AMIN PA, PC, PD, PF, PK, PG, PH, BRES PE PB, PC, PD, PG, PH VDC1, EO COM1 to COM4, S1 to S20 PC, PD, PG, PH, EO PB PE S1 to S20 COM1 to COM4 Ta = -10 to +60C Conditions Ratings -0.3 to +3.0 -0.3 to +4.0 -0.3 to +4.0 -0.3 to VDD1 +0.3 -0.3 to VDD1 +0.3 -0.3 to +7 -0.3 to VDD1 +0.3 -0.3 to VDD4 +0.3 -0.3 to VDD4 +0.3 0 to 3 0 to 1 0 to 2 300 3 100 -10 to +60 -45 to +125 Unit V V V V V V V V V mA mA mA A mA mW C C
Allowable Operating Ranges at Ta = -10 to +60C, VDD = 0.9 to 1.8 V
Parameter Symbol VDD1 Supply voltage VDD3 VDD4 VDD5 VIH1 Input high-level voltage VIH2 VIH3 VIH4 VIL1 Input low-level voltage VIL2 VIL3 VIL4 VIN1 Input amplitude VIN2 VIN3 Input voltage range VIN4 FIN1 FIN2 Input frequency FIN3 FIN4 FIN5 Conditions Voltage applied to the VDD pin Voltage applied to the VDDRAM pin Voltage applied to the VDC3 pin Memory retention voltage Ports PC, PD, PG, PH, and PK Port PA Port PF Port BRES Ports PC, PD, PG, PH, and PK Port PA Port PF Port BRES XIN FMIN, AMIN: VDD1 = 0.9 to 1.8 V FMIN: VDD1 = 0.9 to 1.8 V ADI0, ADI1, ADI3, VDD1 XIN: CI 35 k FMIN: VIN2, VDD1 = 0.9 to 1.8 V FMIN: VIN3, VDD1 = 0.9 to 1.8 V AMIN(L): VIN2, VDD1 = 0.9 to 1.8 V AMIN(H): VIN2, VDD1 = 0.9 to 1.8 V Ratings min 0.9 2.7 2.7 0.5 0.7 VDD1 0.8 VDD1 0.8 VDD1 0.6 VDD1 0 0 0 0 0.5 0.035 0.05 0 70 10 130 0.5 2.0 75 VDD1 VDD1 VDD1 VDD1 0.3 VDD1 0.2 VDD1 0.2 VDD1 0.2 VDD1 0.6 0.35 0.35 VDD4 80 130 250 10 20 V V V V V V V V Vrms Vrms Vrms V kHz MHz MHz MHz MHz typ 1.3 3.0 3.0 max 1.8 3.3 3.3 V Unit
No. 6651-3/12
LC72346W, 72347W Electrical Characteristics under allowable operating conditions
Parameter Symbol IIH1 IIH2 Input high-level current IIH3 IIH4 IIL1 IIL2 Input low-level current IIL3 IIL4 Input floating voltage VIF RPD1 Pull-down resistor values Hysteresis RPD2 VH VOH1 VOH2 VOH3 Output high-level voltage VOH4 VOH5 VOH6 VOH7 VOL1 VOL2 VOL3 Output low-level voltage VOL4 VOL5 VOL6 VOL7 Output off leakage current A/D converter error IDD1 IDD2 Current drain IDD3 IDD4 IOFF1 IOFF2 XOUT: IO = 1 A S1 to S20: IO = 20 A COM1, COM2, COM3, COM4: IO = 100 A VDC1: IO = 1 mA PB: IO = -50 A PC, PD, PG, PH and PK: IO = -1 mA EO: IO = -500 A XOUT: IO = -1 A S1 to S20: IO = -20 A COM1, COM2, COM3, COM4: IO = -100 A PE: IO = 2 mA Ports PB, PC, PD, PG, PK, and EO Port PE ADI0, ADI1, ADI3 VDD1 VDD1 = 1.3 V: FIN2 130 MHz, Ta = 25C VDD1 = 1.3 V: In PLL stop mode, Ta = 25C VDD1 = 1.3 V: In HALT mode, Ta = 25C *1 VDD1 = 1.8 V, with the oscillator stopped, Ta = 25C *2 -3 -100 -1/2 10 0.15 0.1 1 Conditions XIN: VDD1 = 1.3 V FMIN, AMIN: VDD1 = 1.3 V Port PF: VDD1 = 1.3 V PA (without pull-down resistors), the PC, PD, PG, and PH ports, and BRES, PK: VDD1 = 1.3 V XIN: VDD1 = VSS FMIN, AMIN: VDD1 = VSS Port PF: VDD1 = VSS PA (without pull-down resistors), the PC, PD, PG, and PH ports, and BRES, PK: VDD1 = VSS PA (with pull-down resistors) PA/PF (with pull-down resistors), VDD1 = 1.3 V TEST1, TEST2 (with pull-down resistors), VDD1 = 1.3 V BRES PB: IO = 1 mA PC, PD, PG, PH and PK: IO = 1 mA EO: IO = 500 A 0.1 VDD1 VDD1 - 0.3 VDD VDD1 - 0.3 VDD1 VDD4 - 0.3 VDD4 VDD1 - 0.3 VDD1 VDD4 -1 VDD4 -1 VDD4 -1 0.3 VDD1 0.3 VDD1 0.3 VDD4 0.3 VDD1 VDD4 -2 VDD4 -2 0.6 VDD1 +3 +100 +1/2 30 75 100 10 0.2 VDD1 -3 -8 3 8 Ratings min typ max 3 20 4 3 -3 -20 -4 -3 0.05 VDD1 200 Unit A A A A A A A A V k k V V
V V V V V V V V V V V V V A nA LSB mA mA mA A
Note*: The halt mode current drain is due to 20 instructions being executed every 125 ms.
No. 6651-4/12
LC72346W, 72347W *1. Halt and PLL STOP mode current test circuit
7 pF 75 kHz XOUT XIN 7 pF PA, PF, PK VDC3 VSS FMIN AMIN TEST1, 2 VADJ 3V VSS FMIN AMIN TEST1, 2 7 pF VDC3 VADJ 3V VDD RES A
*2. Backup mode current test circuit
7 pF 75 kHz XOUT XIN VDD RES A
With all ports other than those specified above left open. With output mode selected for PC and PD. With segments S13 to S20 selected.
With all ports other than those specified above left open. With output mode selected for PC and PD. With segments S13 to S20 selected.
DC-DC Converter Application
VADJ
VDC3
VDDRAM
VDC1
VSS
VDD
No. 6651-5/12
LC72346W, 72347W Block Diagram
XIN XOUT FMIN AMIN
1/2 1/2
DIVIDER SYSTEM CLOCK GENERATOR 1/2 1/16,1/17
REFERENCE DIVIDER
PHASE DETECTOR
EO
PROGRAMMBLE DIVIDER
1/8
PLL DATA LATCH VSS
1/2
PLL CONTROL
LCDA/B
S1
SEG 4 LA 7 VDC1 VDC3 VADJ RES TEST1 TEST2 PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PC0 PC1 PC2 PC3 INT0/PD0 INT1/PD1 PD2 PD3
* *
Clock Control
LCD 80 PORT DRIVER
LCPA/B
S12 P-ON RESET
RAM 256x4bits (LC72346) 512x4bits (LC72347)
ADDRESS DECODER BANK
DATA LATCH BUS DRIVER DATA LATCH BUS DRIVER
/ /
BUS DRIVER
S13/PH0 S14/PH1 S15/PH2 S16/PH3 S17/PG0 S18/PG1 S19/PG2 S20/PG3
DATA LATCH BUS DRIVER DATA LATCH BUS DRIVER DATA LATCH BUS DRIVER
/ / /
ROM 4kx16bits (LC72346) 6Kx16bits (LC72347)
BUS CONTROL
INSTRUCTION DECODER SKIP JMP CAL RETURN INTERRUPT RESET BANK CF COMMON DRIVER COM4 COM3 COM2 COM1
ADDRESS DECODER 14 ADDRESS COUNTER 14 STACK
BEEP TONE DATA LATCH BUS DRIVER
/
PE0/BEEP MPX PE1
LATCH A SIO LATCH B TIMER 0 ALU
JUDGE
VDDRAM
VDD MPX MPX (6bits)
PK0 SCK1/PK1 SO1/PK2 SI1/PK3
DATA LATCH BUS DRIVER
/
DATA LATCH BUS DRIVER
/
PF0/ADI0 PF1/ADI1 PF2/ADI3
DATA BUS
No. 6651-6/12
LC72346W, 72347W Pin Functions
Pin No. Pin I/O Function I/O circuit
64 1
XIN XOUT
I O
75 kHz oscillator connections
63 2
TEST1 TEST2
I I
IC testing. These pins must be connected to ground.
--
6 5 4 3
PA0 PA1 PA2 PA3 I
Special-purpose ports for key return signal input designed with a low threshold voltage. When a key matrix is formed in combination with port PB, simultaneous multiple key presses with up to 3 keys can be detected. The pull-down resistors are set up for all four pins at the same time with the IOS instruction (PWn = 2.b1). This setting cannot be specified for individual pins. In backup mode, these pins go to the input disabled state, and the pull-down resistors are disabled after a reset.
Input with built-in pull-down resistor
Unbalanced CMOS push-pull 10 9 8 7 PB0 PB1 PB2 PB3 O Unbalanced CMOS outputs. These outputs are switched with the IOS 0 instruction. Since these outputs are unbalanced, no diodes are required to prevent short circuits due to simultaneous multiple key presses. These outputs go to the high-impedance output state in backup mode. After a reset, they go to the high-impedance output state and remain in that state until an output instruction (OUT, SPB, or RPB) is executed.
CMOS push-pull 14 13 12 11 18 17 16 15 PC0 PC1 PC2 PC3 INT1/PD0 INT0/PD1 PD2 PD3 *2 I/O General-purpose I/O ports. PD0, PD1 can be used as an external interrupt port. The IOS instruction (Pwn = 4, 5) is used for switching the general-purpose I/O port function, and these ports can be set to input or output in 1-bit units. (0: input, 1: output) In backup mode they go to the input disabled high-impedance state. After a reset, they switch to the general-purpose input port function.
General-purpose output and beep tone output shared function ports (PE0 only). The BEEP instruction is used to switch PE0 between the general-purpose output port and beep tone output functions. To use PE0 as a general-purpose output port, execute a BEEP instruction with b2 set to 0. Set b2 to 1 to use PE0 as the beep tone output port. The b0 and b1 bits are used to select the beep tone frequency. There are two beep tone frequencies supported. 20 19 BEEP/PE0 PE1 O *: When PE0 is set up as the beep tone output, executing an output instruction to PE0 only changes the state of the internal output latch, it does not affect the beep tone output in any way. Only the PE0 pin can be switched between the general-purpose output function and the beep tone output function; the PE1 pin only functions as a general-purpose output. These pins go to the high-impedance state in backup mode and remain in that state until an output instruction or a BEEP instruction is executed. Since these ports are open-drain ports, resistors must be inserted between these pins and VDD. These ports are set to general-purpose output port function after a reset.
N-channel open-drain
CMOS push-pull Shared function pins used as either general-purpose I/O ports or a serial I/O port. When used as general-purpose I/O ports, the I/O direction can be switched in single pin units with the IOS instruction (with Pwn = C). The IOS instruction (with Pwn = 1, b2) is used to switch the function between the general-purpose I/O port and the serial I/O port function. (0: general-purpose I/O port, 1: serial I/O) In backup mode (low power mode) these pins go to the input disabled highimpedance state. After a reset, the general-purpose input port function is selected.
27 26 25 24
PK0 SCK1/PK1 SO1/PK2 SI1/PK3 I/O
Continued on next page. No. 6651-7/12
LC72346W, 72347W
Continued from preceding page.
Pin No. Pin I/O Function General-purpose input and A/D converter input shared function ports. The IOS instruction (Pwn = FH) is used to switch between the general-purpose input and A/D converter port functions. The general-purpose input and A/D converter port functions can be switched in a units, with 0 specifying general-purpose input, and 1 specifying the A/D converter input function. To select the A/D converter function, set up the A/D converter pin with an IOS instruction with Pwn set to 1. The A/D converter is started with the UCC instruction (b3 = 1, b2 = 1). The ADCE flag is set when the conversion completes. The INR instruction is used to read in the data. *: If an input instruction is executed for one of these pins which is set up for analog input, the read in data will be at the low level since CMOS input is disabled. In backup mode these pins go to the input disabled high-impedance state. These ports are set to their general-purpose input port function after a reset. The A/D converter is a 6-bit successive approximation type converter, and features a conversion time of 1.28 ms. Note that the full-scale A/D converter voltage (3FH) is (63/96) VDD. CMOS push-pull I/O circuit CMOS input/analog input
23 22 21
PF0/ADI0 PF1/ADI1 PF2/ADI3 I
LCD driver segment output and general-purpose I/O shared function ports. The IOS instruction is used for switching between the segment output and generalpurpose I/O functions and between input and output for the general-purpose I/O port function. 33 34 35 36 PG3/S20 PG2/S19 PG1/S18 PG0/S17 O 37 38 39 40 PH3/S16 PH2/S15 PH1/S14 PH0/S13 *2 * When used as segment output ports The general-purpose I/O port function is selected with the IOS instruction (Pwn = 8). b0 = S17 to 20/PG0 to 3 (0: Segment output, 1: PG0 to 3) The general-purpose I/O port function is selected with the IOS instruction (Pwn = 9). b0 = S13 to 16/PH0 to 3 (0: Segment output, 1: PH0 to 3) * When used as general-purpose I/O ports The IOS instruction (Pwn = 6,7) is used to select input or output. Note that the mode can be set in a bit units. b0 = PG0 b1 = PG1 b2 = PG2 b3 = PG3 0: Input 1: Output b0 = PH0 b1 = PH1 b2 = PH2 b3 = PH3 0: Input 1: Output
In backup mode, these pins go to the input disabled high-impedance state if set up as general-purpose outputs, and are fixed at the low level if set up as segment outputs. These ports are set up as segment outputs after a reset. Although the general-purpose port/LCD port setting is a mask option, the IOS instruction must be used as described above to set up the port function. CMOS push-pull LCD driver segment output pins.
41 to 52
A 1/4-duty 1/2-bias drive technique is used. S12 to S1 O The frame frequency is 75 Hz. In backup mode, these outputs are fixed at the low level. After a reset, these outputs are fixed at the low level.
53 54 55 56
COM4 COM3 COM2 COM1 O
LCD driver common output pins. A 1/4-duty 1/2-bias drive technique is used. The frame frequency is 75 Hz. In backup mode, these outputs are fixed at the low level. After a reset, these outputs are fixed at the low level.
Continued on next page.
No. 6651-8/12
LC72346W, 72347W
Continued from preceding page.
Pin No. Pin I/O System reset input. 57 RES I In CPU operating mode or halt mode, applications must apply a low level for at least one full machine cycle to reset the system and restart execution with the PC set to location 0. This pin is connected in parallel with the internal power on reset circuit. Output for the 3 V step-up circuit clock. Outputs 1/2 the AM local oscillator frequency in AM reception mode, and 1/256 the FM local oscillator or 75 kHz in FM reception mode. Voltage stepped up by the DC-DC converter (3 V) May also be used to input an equivalent voltage. RAM backup power supply. Connected to the VDC3 voltage through a diode. VDC3 voltage adjustment pin. Insert a 10 k trimmer between this pin and ground to adjust the VDC3 voltage. CMOS amplifier input FM VCO (local oscillator) input. 59 FMIN I This pin is selected with the PLL instruction CW1. The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode. Function I/O circuit
31
VDC1
O
30
VDC3
I
29
VDDRAM
I
32
VADJ
O
AM VCO (local oscillator) input. This pin and the bandwidth are selected with the PLL instruction CW1. CW1 b1, b0 60 AMIN I 1 1 0 1 Input pins AMIN (H) FMIN (L) Bandwidth 2 to 20 MHz (SW) 0.5 to 10 MHz (MW, LW)
CMOS amplifier input
The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode. CMOS push-pull Main charge pump output. When the local oscillator frequency divided by N is higher than the reference frequency a high level is output, when lower, a low level is output,and the pin is set to the high-impedance state when the frequencies match. This output goes to the high-impedance state in backup mode, in halt mode, after a reset, and in PLL stop mode.
62
EO
O
61 28 58
VSS VSS VDD --
Power supply pin.
This pin must be connected to ground. This pin must be connected to ground. This pin must be connected to VDD. Supports A/D converter. --
Note*: When a pin in an I/O switching port is used as an output, applications must first set up the data with an OUT, SPB, or RPB instruction and then set up output mode with an IOS instruction.
No. 6651-9/12
LC72346W, 72347W LC72346/347 Series Instruction Set Terminology ADDR b C DH DL I M N Rn Pn PW r ( ), [ ] M (DH, DL) : Program memory address : Borrow : Carry : Data memory address High (Row address) [2 bits] : Data memory address Low (Column address) [4 bits] : Immediate data [4 bits] : Data memory address : Bit position [4 bits] : Resister number [4 bits] : Port number [4 bits] : Port control word number [4 bits] : General register (One of the addresses from 00H to 0FH of BANK0) : Contents of register or memory : Data memory specified by DH, DL
Instruction group
Mnemonic AD ADS
Operand 1st r r r r M M M M r r r r M M M M r M M r M M 2nd M M M M I I I I M M M M I I I I M I I M I I Add M to r
Function
Operations function R (r) + (M) R (r) + (M) + C R (r) + (M) + C skip if carry M (M) + I M (M) + I, skip if carry M (M) + I + C M (M) + I + C, skip if carry R (r) - (M) R (r) - (M), skip if borrow R (r) - (M) - b R (r) - (M) - b, skip if borrow M (M) - I M (M) - I, skip if borrow M (M) - I - b M (M) - I - b, skip if borrow (r) - (M), skip if zero (M) - I, skip if zero (M) - I, skip if not zero (r) - (M), skip if not borrow (M) - I, skip if not borrow (M) - I, skip if borrow
Instruction format f 0 e 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 d 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 c 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 1 1 0 b 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 1 1 a 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 1 9 8 7 6 5 4 3 2 r r r r I I I I r r r r I I I I r I I r I I 1 0
DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH
DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL
Add M to r, then skip if carry Add M to r with carry Add M to r with carry, then skip if carry Add I to M Add I to M, then skip if carry Add I to M with carry Add I to M with carry, then skip if carry Subtract M from r Subtract M from r, then skip if borrow Subtract M from r with borrow Subtract M from r with borrow, then skip if borrow Subtract I from M Subtract I from M, then skip if borrow Subtract I from M with borrow Subtract I from M with borrow, then skip if borrow Skip if r equal to M Skip if M equal to I Skip if M not equal to I Skip if r is greater than or equal to M Skip if M is greater than equal to I Skip if M is less than I
R (r) + (M), skip if carry 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Addition instructions
AC ACS AI AIS AIC AICS SU SUS
Subtraction instructions
SB SBS SI SIS SIB SIBS
Comparison instructions
SEQ SEQI SNEI SGE SGEI SLEI
Continued on next page.
No. 6651-10/12
LC72346W, 72347W
Continued from preceding page.
Instruction group
Mnemonic AND ANDI OR ORI EXL EXLI SHR LD
Operand 1st r M r M r M r r M r M M1 M M M M r M r M2 I N N 2nd M I M I M I
Function AND M with r AND I with M OR M with r OR I with M Exclusive OR M with r Exclusive OR M with M Shift r right with carry Load M to r Store r to M Move M to destination M referring to r in the same row Move source M referring to r to M in the same row Move M to M in the same row Move I to M Test M bits, then skip if all bits specified are true Test M bits, then skip if all bits specified are false Jump to the address Call subroutine Return from subroutine Return from interrupt
Operations function R (r) AND (M) M (M) AND I R (r) OR (M) M (M) OR I R (r) XOR (M) M (M) XOR I carry (r) R (M) M (r) [DH, Rn] (M) M [DH, Rn] [DH, DL1] [DH, DL2] MI if M (N) = all 1, then skip if M (N) = all 0, then skip PC ADDR PC ADDR Stack (PC) + 1 PC Stack PC Stack, BANK Stack, CARRY Stack (Status W-reg) N 1 (Status W-reg) N 0
Instruction format f 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 e 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 d 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 1 0 0 1 1 1 1 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 1 0 0 1 1 1 1 0 c 0 0 0 0 1 1 0 1 1 1 1 0 0 1 1 b 0 0 1 1 0 1 0 0 0 1 1 0 0 0 0 a 0 1 0 1 0 0 0 0 1 0 1 0 1 0 1 9 8 7 6 5 4 3 2 r I r I r I 0 r r r r r DL2 I N N 1 0
Logic operation instructions
DH DH DH DH DH DH 0 0 1
DL DL DL DL DL DL 1 1
DH DH DH DH DH DH DH DH
DL DL DL DL DL1 DL DL DL
Transfer instructions
ST MVRD MVRS MVSR MVI
Bit test instructions
TMT TMF JMP CAL RT RTI SS
Jump and subroutine call instructions
ADDR ADDR
ADDR (13 bits) ADDR (13 bits) 0 0 1 1 1 1 0 1 1 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 1 N N N N N r I2 0 1 1 1 0 1 0 0 1 0 I I I I I N Pn Pn Pn Rn N N N N
SWR SWR SRR SRR N M I1 I I I I I PWn M M M M
N N N N
Set status register Reset status register Test status register true Test status register false Test Unlock F/F Load M to PLL register
0 SWR 1 SWR SRR SRR 0 1
Status register instructions
RS TST TSF TUL
If (Status R-reg) N = all 1, 1 then skip If (Status R-reg) N = all 0, 1 then skip If Unlock F/F (N) = All 0, then skip PLL reg PLL data SIO reg I1, I2 UCCW1 I UCCW2 I BEEP reg I DZC reg I Timer reg I IOS reg PWn N M (Pn) Pn M M (Pn reg) Rn reg (M) (Pn)N 1 (Pn)N 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1
Hardware control instructions
PLL SIO UCS UCC BEEP DZC TMS IOS IN OUT INR
DH 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1
DL I1 0 0 1 0 1
I2
Serial I/O control Set I to UCCW1 Set I to UCCW2 Beep control Dead zone control Set timer register
N Pn Pn Rn Rn N N N N
Set port control word Input port data to M Output contents of M to port Input register/port data to M Output contents of M to register/port Set port1 bits Reset port1 bits
PWn DL DL DL DL Pn Pn Pn Pn
DH DH DH DH 1 1 0 0 0 1 0 1
I/O instructions
OUTR SPB RPB TPT TPF
Test port1 bits, then skip if all bits If (Pn)N = all 1, then skip specified are true Test port1 bits, then skip if all bits If (Pn)N = all 0, then skip specified are false BANK I
Bank switching instructions
BANK
I
Select Bank
0
0
0
0
0
0
0
0
0
1
1
1
I
Continued on next page.
No. 6651-11/12
LC72346W, 72347W
Continued from preceding page.
Instruction group
Mnemonic LCDA LCDB LCPA LCPB HALT CKSTP NOP
Operand 1st M M M M I 2nd I I I I
Function Output segment pattern to LCD digit direct Output segment pattern to LCD digit through LA Halt mode control Clock stop No operation
Operations function LCD (DIGIT) M LCD (DIGIT) LA M HALT reg I, then CPU clock stop Stop x'tal OSC No operation
Instruction format f 1 1 1 1 0 0 0 e 1 1 1 1 0 0 0 d 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 b 0 0 1 1 0 0 0 a 0 1 0 1 0 0 0 9 8 7 6 5 4 3 2 1 0
LCD instructions
DH DH DH DH 0 0 0 0 0 0 0 0 0
DL DL DL DL 1 1 0 0 0 0 0 1 0
DIGIT DIGIT DIGIT DIGIT I
Other instructions
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of November, 2001. Specifications and information herein are subject to change without notice. PS No. 6651-12/12

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